我們的任意頻率、任意輸出格式Si5360、Si5391、Si5341、Si5340時(shí)鐘石英振蕩器將寬帶PLL與專(zhuān)有的多同步小數(shù)合成技術(shù)相結(jié)合，提供多功能、超低抖動(dòng)時(shí)鐘發(fā)生器平臺(tái)。憑借高度靈活的架構(gòu)，時(shí)鐘發(fā)生器能夠在多達(dá)18路差分時(shí)鐘輸出上合成高達(dá)1300 MHz的各種整數(shù)和非整數(shù)相關(guān)頻率組合，同時(shí)提供55 fs RMS相位抖動(dòng)性能，0 ppm誤差。

The Si5360 clock generator for high-speed networking, data center and communications equipment complements Skyworks’ current market leading Si5391/5341/5332 line of clock generators delivering higher levels of jitter performance with a greater number of clock outputs.

The Si5360 clock generator combines Skyworks’ 5^th generation DSPLL™ and MultiSynth™ technologies with an ultra-low jitter VCO to deliver outstanding 55 fs RMS phase jitter reference clocks for high-performance applications like 112G/224G PAM-4 SerDes and Coherent Optics that are used in 400G/600G/800G/1.2Tb Ethernet communications and data center equipment.

The Si5360 is used in applications that demand the highest level of integration and jitter performance. All PLL components are integrated on-chip, reducing the risk of noise coupling associated with discrete solutions and greatly simplifying the clock solution design.

The Si5360 architecture has a one DSPLL with 2 MultiSynths enabling the capability of generating combinations of clock output frequencies that are integer- and non-integer related.

Features 

• Generates any mix of output frequencies
• Ultra-low jitter [12kHz -20MHz] – 55 fs (int) ; 64 fs (frac)
• Total outputs: 18
• Glitch-less, on-the-fly output frequency changes 
• Configurable outputs: LVPECL, LVDS, S-LVDS, CML, HCSL, or LVCMOS
• Simplified API to replace complicated register read/writes (Frequency-on-the-fly/DCO, register status reads)

Applications

• 400/600/800G/1.2T Switches
• 56G/112G/224G PAM4 SerDes clocking
• Data center Switches/NIC/Edge Computing/Accelerator cards
• Clocking for FPGAs, PHYs, memory
• Clock tree generation replacing XOs, buffers, signal format translators
• Test/measurement equipment